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quad, 12-/14-/16-bit nano dacs ? with 5ppm/c on-chip ref, i 2 c interface preliminary technical data ad5625r/ad5645r/ad5665r ad5625/ad5665 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features low power, smallest pin-compatible, quad nano dacs ad5625r/ad5645r/ad5665r 12-/14-/16 bits on-chip 1.25 v/2.5 v, 5 ppm/c reference. ad5625/ad5665 12-/16 bits external reference only 3 mm x 3 mm lfcsp and 14-lead tssop 2.7 v to 5.5 v power supply guaranteed monotonic by design power-on reset to zero scale/midscale per channel power-down i 2 c-compatible serial interface supports standard (100 khz), fast (400 khz), and high speed (3.4 mhz) modes applications process control data acquisition systems portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators addr1 scl sda input register input register input register input register dac register dac register dac register dac register buffer buffer buffer buffer v outa v outb v outc v outd 1.25v/2.5v ref v dd gnd v refin / v refout ad5625r/ad5645r/ad5665r power-down logic string dac d string dac c string dac b string dac a interface logic ldac clr por power-on reset addr2 note. the following pins are available only on 14-pin package - addr2, ldac, clr, por. addr1 scl sda input register input register input register input register dac register dac register dac register dac register buffer buffer buffer buffer v outa v outb v outc v outd v dd gnd v refin ad5625/ad5665 power-down logic string dac d string dac c string dac b string dac a interface logic ldac clr por power-on reset addr2 note. the following pins are available only on 14-pin package - addr2, ldac, clr, por. figure 1. functional block diagrams general description the ad5625r/ad5645r/ad5665r, ad5625/ad5665 members of the nano dac family, are low power, quad, 12-, 14-, 16-bit buffered voltage-out dacs with/without an on-chip reference. all devices operate from a single 2.7 v to 5.5 v supply, are guaranteed monotonic by design and have an i 2 c- compatible serial interface . the ad5625r/ad5645r/ad5665r have an on-chip reference. the ad56x5rbcpz have a 1.25 v, 5 ppm/c reference, giving a full-scale output range of 2.5 v; the ad56x5rbruz have a 2.5 v, 5 ppm/c reference giving a full-scale output range of 5 v. the on-chip reference is off at power-up, allowing the use of an external reference. the internal reference is enabled via a software write. the ad5665 and ad5625 require an external reference voltage to set the output range of the dac. the part incorporates a power-on reset circuit that ensures the dac output powers up to 0 v or midscale and remains there until a valid write takes place. the part contains a per-channel power-down feature that reduces the current consumption of the device to 480 na at 5 v and provides software-selectable output loads while in power-down mode. the low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. the on-chip precision output amplifier enables rail-to-rail output swing. the ad5625r/ad5645r/ad5665r, ad5625/ad5665 use a 2- wire i 2 c-compatible serial interface that operates in standard (100 khz), fast (400 khz), and hi gh speed (3.4 mhz) modes. table 1. related devices part no. description ad5624r/ad5644r/ad5664r ad5624/ad5664 quad spi 12-, 14-, 16-bit dacs, with/without internal reference. ad5627r/ad5647r/ad5667r ad5627/5667, dual i 2 c 12-, 14-,16-bit dacs, with/without internal reference. ad5666 2.7 v to 5.5 v, quad 16-bit dac, internal r eference, spi interface
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 2 of 32 table of contents features...................................................................................1 applications ...........................................................................1 general description .............................................................1 product highlights................................................................1 table1. related devices ........................................................2 table of contents ......................................................2 specifications .........................................................................3 ac characteristics ................................................................4 i 2 c timing specifications.....................................................5 absolute maximum ratings ................................................7 pin configuration and function descriptions..................8 typical performance characteristics ..................................9 terminology...........................................................................17 theory of operation .............................................................19 d/a section............................................................................19 resistor string........................................................................19 output amplifier...................................................................19 internal reference .................................................................19 external reference ................................................................19 serial interface .......................................................................19 write operation.....................................................................21 read operation......................................................................21 high speed mode ..................................................................22 multiple byte write ...............................................................23 broadcast mode .....................................................................23 input shift register................................................................23 write commands and ldac...............................................24 ldac setup............................................................................24 ldac pin.................................................................................25 power-down modes..............................................................25 power-on reset and software reset ....................................26 internal reference setup.......................................................26 clear pin ( clr ) .....................................................................26 applications............................................................................27 using a reference as power supply ....................................27 bipolar operation..................................................................27 power supply bypassing and grounding ...........................27 outline dimensions ..............................................................28 ordering information ...........................................................29 revision history 4/06revision 0: initial version
preliminary technical data ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. pra. | page 3 of 32 specifications: ad5625r /ad5645r/ad5665r, ad5625/ad5665 v dd = 2.7 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max , unless otherwise noted. table 2. b grade 1 parameter min typ max unit conditions/comments static performance 2 ad5665r/ad5665 resolution 16 bits relative accuracy 8 16 lsb differential nonlinearity 1 lsb guaranteed monotonic by design ad5645r resolution 14 bits relative accuracy 2 4 lsb differential nonlinearity 0.5 lsb guaranteed monotonic by design ad5625r/ad5625 resolution 12 bits relative accuracy 0.5 1 lsb differential nonlinearity 0.25 lsb guaranteed monotonic by design zero-code error 2 10 mv all zeroes loaded to dac register offset error 1 10 mv full-scale error ?0.1 1 % of fsr all ones loaded to dac register gain error 1.5 % of fsr zero-code error drift 2 v/c gain temperature 2.5 ppm of fsr/c dc power supply rejection ?100 db dac code = midscale ; v dd = 5v 10% dc crosstalk (external reference) 10 v due to full-scale output change, 10 v/ma due to load current change 5 v due to powering down (per channel) dc crosstalk (internal reference) 25 v due to full-scale output change, r l = 2 k? to gnd or v dd 20 v/ma due to load current change 10 v due to powering down (per channel) output characteristics 3 output voltage range 0 v dd v capacitive load stability 2 nf r l = 10 nf r l = 2 k? dc output impedance 0.5 ? short-circuit current 30 ma v dd = 5 v power-up time 4
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 4 of 32 b grade 1 parameter min typ max unit conditions/comments logic inputs (sda, scl) i in , input current 1 a v inl , input low voltage 0.3 v dd v v inh , input high voltage 0.7 v dd v c in , pin capacitance 2 pf v hyst , input hysteresis 0.1 v dd v logic outputs (open drain) v ol , output low voltage 0.4 v i sink = 3 ma 0.6 v i sink = 6 ma floating-state leakage current 1 a floating-state output 2 pf power requirements v dd 2.7 5.5 v i dd (normal mode) 4 v ih = v dd , v il = gnd v dd = 4.5 v to 5.5 v 0.45 0.55 ma internal reference off v dd = 2.7 v to 3.6 v 0.44 0.5 ma internal reference off v dd = 4.5 v to 5.5 v 0.95 1.2 ma internal reference on v dd = 2.7 v to 3.6 v 0.95 1.15 ma internal reference on i dd (all power-down modes) 5 0.48 1 a v ih = v dd , v il = gnd 1 temperature range: b grade: ?40c to +105c. 2 linearity calculated using a reduced code range: ad5665 (c ode 512 to code 65,024); ad5645 (co de 128 to code 16,256); ad5625 (c ode 32 to code 4064). output unloaded. 3 guaranteed by design and characterization, not production tested. 4 interface inactive. all dacs active. dac outputs unloaded. 5 all dacs powered down. ac characteristics v dd = 2.7 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max , unless otherwise noted. 1 table 4. parameter 2 min typ max unit conditions/comments 3 output voltage settling time ad5625r/ad5625 3 4.5 s ? to ? scale settling to 0.5 lsb ad5645r 3.5 5 s ? to ? scale settling to 0.5 lsb ad5665r/ad5665 4 7 s ? to ? scale settling to 2 lsb slew rate 1.8 v/s digital-to-analog glitch impulse 10 nv-s 1 lsb change around major carry digital feedthrough 0.1 nv-s reference feedthrough ?90 dbs v ref = 2 v 0.1 v p-p, frequency 10 hz to 20 mhz digital crosstalk 0.1 nv-s analog crosstalk 1 nv-s external reference 4 nv-s internal reference dac-to-dac crosstalk 1 nv-s external reference 4 nv-s internal reference multiplying bandwidth 340 khz v ref = 2 v 0.1 v p-p total harmonic distortion ?80 db v ref = 2 v 0.1 v p-p, frequency = 10 khz output noise spectral density 120 nv/hz dac code = midscale, 1 khz 100 nv/hz dac code = midscale, 10 khz output noise 15 v p-p 0.1 hz to 10 hz 1 guaranteed by design and characterization, not production tested. 2 see the terminology section.
preliminary technical data ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. pra. | page 5 of 32 3 temperature range is ?40c to +105c, typi cal at 25c.
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 6 of 32 i 2 c timing specifications v dd = 2.7 v to 5.5 v; all specifications t min to t max , f scl = 3.4 mhz, unless otherwise noted. 1 table 5. limit at t min , t max parameter conditions 2 min max unit description f scl3 standard mode 100 khz serial clock frequency fast mode 400 khz high speed mode, c b = 100 pf 3.4 mhz high speed mode, c b = 400 pf 1.7 mhz t 1 standard mode 4 s t high , scl high time fast mode 0.6 s high speed mode, c b = 100 pf 60 ns high speed mode, c b = 400 pf 120 ns t 2 standard mode 4.7 s t low , scl low time fast mode 1.3 s high speed mode, c b = 100 pf 160 ns high speed mode, c b = 400 pf 320 ns t 3 standard mode 250 ns t su;dat , data setup time fast mode 100 ns high speed mode 10 ns t 4 standard mode 0 3.45 s t hd;dat , data hold time fast mode 0 0.9 s high speed mode, c b = 100 pf 0 70 ns high speed mode, c b = 400 pf 0 150 ns t 5 standard mode 4.7 s t su;sta, set-up time for a repeated start condition fast mode 0.6 s high speed mode 160 ns t 6 standard mode 4 s t hd;sta , hold time (repeated) start condition fast mode 0.6 s high speed mode 160 ns t 7 standard mode 4.7 s t buf , bus free time between a stop and a start condition fast mode 1.3 s t 8 standard mode 4 s t su;sto , setup time for a stop condition fast mode 0.6 s high speed mode 160 ns t 9 standard mode 1000 ns t rda , rise time of sda signal fast mode 300 ns high speed mode, c b = 100 pf 10 80 ns high speed mode, c b = 400 pf 20 160 ns t 10 standard mode 300 ns t fda , fall time of sda signal fast mode 300 ns high speed mode, c b = 100 pf 10 80 ns high speed mode, c b = 400 pf 20 160 ns t 11 standard mode 1000 ns t rcl , rise time of scl signal fast mode 300 ns high speed mode, c b = 100 pf 10 40 ns high speed mode, c b = 400 pf 20 80 ns t 11a standard mode 1000 ns t rcl1 , rise time of scl signal after a repeated start condition and after an acknowledge bit fast mode 300 ns high speed mode, c b = 100 pf 10 80 ns high speed mode, c b = 400 pf 20 160 ns
preliminary technical data ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. pra. | page 7 of 32 limit at t min , t max parameter conditions 2 min max unit description t 12 standard mode 300 ns t fcl , fall time of scl signal fast mode 300 ns high speed mode, c b = 100 pf 10 40 ns high speed mode, c b = 400 pf 20 80 ns t sp4 fast mode 0 50 ns pulse width of spike suppressed high speed mode 0 10 ns 1 see figure 2. high speed mode timin g specification applies only to the ad5625bruz-2 and ad5665bruz-2. 2 cb refers to the capacitance on the bus line. 3 the sda and scl timing is measured with the input filters enabled. switching off the input filter s improves the transfer rate b ut has a negative effect on emc behavior of the part. 4 input filtering on the scl and sda inputs suppress noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode. figure 2. 2-wire serial interface timing diagram
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 8 of 32 absolute maximum ratings t a = 25c, unless otherwise noted. table 6. parameter rating v dd to gnd ?0.3 v to +7 v v out to gnd ?0.3 v to v dd + 0.3 v v refin /v refout to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max) 150c power dissipation (t j max ? t a )/ ja lfcsp_wd package (4-layer board) ja thermal impedance 61c/w tssop package ja thermal impedance 150.4c/w reflow soldering peak temperature pb-free 260c 5c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. pra. | page 9 of 32 pin configuration and fu nction descriptions ldac addr1 v dd v out a v out c por v refin/ v refout scl sda gnd v out b v out d clr addr2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 ad5625(r) ad5645r ad5665(r) top view (not to scale) note: v refout only on -r versions v out a v out b gnd v out c v out d v refin/ v refout v dd sda scl addr 1 2 3 4 5 10 9 8 7 6 ad5625(r) ad5645r ad5665(r) top view (not to scale) note: v refout only on -r versions pin configuration (14-pin) pin configuration (10-pin) figure 3. pin configurations table 7. pin function descriptions pin no. (14-pin) pin no. (10-pin) mnemonic description 1 n/a ldac active low load dac pin. 2 n/a addr1 three-state address input. sets the two least significant bits (bit a1, bit a0) of the 7-bit slave address (see table 6). 3 9 v dd power supply input. these parts can be operate d from 2.7 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in para llel with a 0.1 f capacitor to gnd. 4 1 v out a analog output voltage from dac c. the outp ut amplifier has rail-to-rail operation. 5 4 v out c analog output voltage from dac d. the outp ut amplifier has rail-to-rail operation. 6 n/a por power-on reset. 7 10 v refin /v refout the ad5625r/ad5645r/ad5665r, ad5625/ad5665 have a common pin for reference input and reference output. the internal reference and reference output are only available on suffix -- -r versions. when using the internal reference, this is the reference output pin. when using an external reference, this is the reference input pin. the default for this pin is as a reference input. 8 n/a addr2 three-state address input. sets bits a3 and a2 of the 7-bit slave address (see table 6). 9 n/a clr asynchronous cl ear input. the clr input is falling edge sensitive. . while clr is low, all ldac pulses are ignored. when clr is activated, zero scale is loaded to all input and dac registers. this clears the output to 0 v. the part exits clear code mode on the 24th falling edge of the next write to the part. if clr is activated during a write sequence, the write is aborted. 10 5 v out d analog output voltage from dac a. the outp ut amplifier has rail-to-rail operation. 11 2 v out b analog output voltage from dac b. the o utput amplifier has rail-to-rail operation. 12 3 gnd ground reference point for all circuitry on the part. 13 8 sda serial data line. this is used in conjunction with the scl line to clock data into or out of the 16-bit input register. it is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. 14 7 scl serial clock line. this is used in conjunction wi th the sda line to clock data into or out of the 16-bit input register. n/a 6 addr three-state address input. sets the two least sign ificant bits (bit a1, bit a0) of the 7-bit slave address.
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 10 of 32 typical performance characteristics code inl error (lsb) 10 4 6 8 0 2 ?6 ?10 ?8 ?2 ?4 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k v dd = v ref = 5v t a = 25c 05858-005 figure 4. inl ad5665, external reference code inl error (lsb) 4 ?4 0 2500 5000 7500 10000 12500 15000 05856-005 ?3 ?2 ?1 0 1 2 3 v dd = v ref = 5v t a = 25c figure 5. inl ad5645, external reference code inl error (lsb) 1.0 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 05856-006 ?0.8 ?0.6 ?0.4 0 0.4 0.2 ?0.2 0.6 0.8 v dd = v ref = 5v t a = 25c figure 6. inl ad5625, external reference code dnl error (lsb) 1.0 0.6 0.4 0.2 0.8 0 ?0.4 ?0.2 ?0.6 ?1.0 ?0.8 0 10k 20k 30k 40k 50k 60k 05856-007 v dd = v ref = 5v t a = 25c figure 7. dnl ad5665, external reference dnl error (lsb) 0.5 0.3 0.2 0.1 0.4 0 ?0.2 ?0.1 ?0.3 ?0.5 ?0.4 05856-008 v dd = v ref = 5v t a = 25c code 0 2500 5000 7500 10000 12500 15000 figure 8. dnl ad5645, external reference dnl error (lsb) 0.20 0.10 0.05 0.15 0 ?0.05 ?0.10 ?0.20 ?0.15 05856-009 code 0 500 1000 1500 2000 2500 3000 3500 4000 v dd = v ref = 5v t a = 25c figure 9. dnl ad5625, external reference
preliminary technical data ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. pra. | page 11 of 32 code inl error (lsb) 10 8 0 ?10 ?6 ?8 ?4 6 ?2 4 2 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 5v v refout = 2.5v t a = 25c 05856-010 figure 10. inl ad5665r, 2.5v internal reference code inl error (lsb) 4 3 ?4 ?3 ?2 2 ?1 1 0 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 v dd =5v v refout =2.5v t a = 25c 05856-011 figure 11. inl ad5645r, 2.5v internal reference code inl error (lsb) 1.0 0.8 0 ?1.0 ?0.8 ?0.6 0.6 ?0.4 ?0.2 0.4 0.2 0 1000 500 2000 1500 3500 3000 2500 4000 v dd =5v v refout =2.5v t a = 25c 05856-012 figure 12. inl ad5625r, 2.v5 internal reference code dnl error (lsb) 1.0 0.8 0 ?1.0 ?0.6 ?0.8 ?0.4 0.6 ?0.2 0.4 0.2 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd =5v v refout =2.5v t a =25c 05856-013 figure 13. dnl ad5665r, 2.5v internal reference code dnl error (lsb) 0.5 0.4 0 ?0.5 ?0.3 ?0.4 ?0.2 0.3 ?0.1 0.2 0.1 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 v dd = 5v v refout = 2.5v t a = 25c 05856-014 figure 14. dnl ad5645r, 2.5v internal reference code dnl error (lsb) 0.20 0.15 0 ?0.20 ?0.15 ?0.10 0.10 ?0.05 0.05 0 1000 500 2000 1500 3500 3000 2500 4000 v dd = 5v v refout = 2.5v t a = 25c 05856-015 figure 15. dnl ad5625r, 2.5v internal reference
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 12 of 32 code inl error (lsb) 10 8 4 6 2 0 ?4 ?2 ?6 ?8 ?10 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 05856-016 v dd = 3v v refout = 1.25v t a = 25c figure 16. inl ad5665r,1.25v internal reference code inl error (lsb) 4 ?4 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 05856-017 3 2 1 0 ?1 ?2 ?3 v dd = 3v v refout = 1.25v t a = 25c figure 17. inl ad5645r, 1.25v internal reference code inl error (lsb) 1.0 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 0.8 0.6 0.4 0.2 ?0.2 ?0.4 ?0.6 ?0.8 v dd = 3v v refout = 1.25v t a = 25c 05856-018 figure 18. inl ad5625r,1.25v internal reference code dnl error (lsb) 1.0 0.8 0.4 0.6 0.2 0 ?0.4 ?0.2 ?0.6 ?0.8 ?1.0 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 3v v refout = 1.25v t a = 25c 05856-019 figure 19. dnl ad5665r,1.25v internal reference code dnl error (lsb) 0.5 ?0.5 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 0 0.4 0.3 0.2 0.1 ?0.1 ?0.2 ?0.3 ?0.4 v dd = 3v v refout = 1.25v t a = 25c 05856-020 figure 20. dnl ad5645r,1.25v internal reference code dnl error (lsb) 0.20 ?0.20 0 500 1000 1500 2000 2500 3000 3500 4000 0 0.15 0.10 0.05 ?0.05 ?0.10 ?0.15 v dd = 3v v refout = 1.25v t a = 25c 05856-021 figure 21. dnl ad5625r, 1.25v internal reference
preliminary technical data ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. pra. | page 13 of 32 temperature (c) error (lsb) 8 6 4 2 ?6 ?4 ?2 0 ?8 ?40 ?20 40 20 0 100 80 60 05856-022 min dnl max dnl max inl min inl v dd = v ref = 5v figure 22. inl error and dnl error vs. temperature v ref (v) error (lsb) 10 4 6 8 2 0 ?8 ?6 ?4 ?2 ?10 0.75 1.25 1.75 2.25 4.25 3.75 3.25 2.75 4.75 min dnl max dnl max inl min inl v dd = 5v t a = 25c 05856-023 figure 23. inl and dnl error vs. v ref v dd (v) error (lsb) 8 6 4 2 ?6 ?4 ?2 0 ?8 2.7 3.2 3.7 4.7 4.2 5.2 min dnl max dnl max inl min inl t a = 25c 05856-024 figure 24. inl and dnl error vs. supply temperature (c) error (% fsr) 0 ?0.04 ?0.02 ?0.06 ?0.08 ?0.10 ?0.18 ?0.16 ?0.14 ?0.12 ?0.20 ?40 ?20 40 20 0 100 80 60 v dd = 5v gain error full-scale error 05856-025 figure 25. gain error and full-scale error vs. temperature temperature (c) error (mv) 1.5 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 ?40 ?20 40 20 080 60 100 offset error zero-scale error 05856-026 figure 26. zero-scale error and offset error vs. temperature v dd (v) error (% fsr) 1.0 ?1.5 ?1.0 ?0.5 0 0.5 ?2.0 2.7 3.2 3.7 4.7 4.2 5.2 gain error full-scale error 05856-027 figure 27. gain error and full-scale error vs. supply
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 14 of 32 v dd (v) error (mv) 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 2.7 3.2 4.2 3.7 5.2 4.7 zero-scale error offset error t a = 25c 05856-028 figure 28. zero-scale error and offset error vs. supply i dd (ma) frequency 0 1 2 3 4 5 6 0.41 0.42 0.43 0.44 0.45 05856-029 v dd = 5.5v t a = 25c figure 29. i dd histogram with external reference, 5.5 v i dd (ma) frequen c y 0 1 2 3 4 5 6 0.92 0.94 0.96 0.98 05856-030 v dd = 5.5v t a = 25c figure 30. i dd histogram with internal reference, v refout = 2.5 v i dd (ma) frequency 0 1 2 3 5 4 6 8 7 0.39 0.40 0.41 0.42 0.43 05856-060 v dd = 3.6v t a = 25c figure 31. i dd histogram with external reference, 3.6 v i dd (ma) frequency 0 1 2 3 5 4 6 8 7 0.90 0.92 0.94 0.96 05856-061 v dd = 3.6v t a = 25c figure 32. i dd histogram with internal reference, v refout = 1.25 v current (ma) error voltage (v) 0.5 0.4 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 ?10 ?8 ?6 ?4 ?2 0 2 4 8 610 v dd = 3v v refout = 1.25v v dd = 5v v refout = 2.5v dac loaded with zero-scale sinking current dac loaded with full-scale sourcing current 0 5856-031 figure 33. headroom at rails vs. source and sink
preliminary technical data ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. pra. | page 15 of 32 current (ma) v out (v) 6 5 4 3 2 1 ?1 0 ?30 ?20 ?10 0 10 20 30 v dd = 5v v refout = 2.5v t a = 25c zero scale full scale midscale 1/4 scale 3/4 scale 0 5856-046 figure 34. ad56x5r with 2.5v reference, source and sink capability current (ma) v out (v) 4 ?1 0 1 2 3 ?30 ?20 ?10 0 10 20 30 v dd = 3v v refout = 1.25v t a = 25c zero scale full scale midscale 1/4 scale 3/4 scale 0 5856-047 figure 35. ad56x5r with 1.25v reference, source and sink capability temperature (c) i dd (ma) 0.50 0.05 0.10 0.15 0.20 0.35 0.40 0.25 0.30 0.45 0 ?40 ?20 0 20 40 60 80 100 05856-063 t a = 25c v dd = v refin = 5v v dd = v refin = 3v figure 36. supply current vs. temperature time base = 4s/div v dd = v ref = 5v t a = 25c full-scale code change 0x0000 to 0xffff output loaded with 2k ? and 200pf to gnd v out = 909mv/div 1 05856-048 figure 37. full-scale settling time, 5 v ch1 2.0v ch2 500mv m100s 125ms/s a ch1 1.28v 8.0ns/pt v dd = v ref = 5v t a = 25c v out v dd 1 2 max(c2) 420.0mv 05856-049 figure 38. power-on reset to 0 v 05856-050 v dd = 5v sync slck v out 1 3 ch1 5.0v ch3 5.0v ch2 500mv m400ns a ch1 1.4v 2 figure 39. exiting power-down to midscale
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 16 of 32 sample number v out (v) 2.521 2.522 2.523 2.524 2.525 2.526 2.527 2.528 2.529 2.530 2.531 2.532 2.533 2.534 2.535 2.536 2.537 2.538 0 50 100 150 350 400 200 250 300 450 512 05856-058 v dd = v ref = 5v t a = 25c 5ns/sample number glitch impulse = 9.494nv 1lsb change around midscale (0x8000 to 0x7fff) figure 40. digital-to-analog glitch impulse (negative) sample number v out (v) 2.491 2.492 2.493 2.494 2.495 2.496 2.497 2.498 0 50 100 150 350 400 200 250 300 450 512 05856-059 v dd = v ref = 5v t a = 25c 5ns/sample number analog crosstalk = 0.424nv figure 41. analog crosstalk, external reference sample number v out (v) 2.456 2.458 2.460 2.462 2.464 2.466 2.468 2.470 2.472 2.474 2.476 2.478 2.480 2.482 2.484 2.486 2.488 2.490 2.492 2.494 2.496 0 50 100 150 350 400 200 250 300 450 512 05856-062 v dd = 5v v refout = 2.5v t a = 25c 5ns/sample number analog crosstalk = 4.462nv figure 42. analog crosstalk, internal reference 1 y axis = 2v/div x axis = 4s/div v dd = v ref = 5v t a = 25c dac loaded with midscale 05856-051 figure 43. 0.1 hz to 10 hz output noise plot, external reference 5s/div 10v/div 1 v dd = 5v v refout = 2.5v t a = 25c dac loaded with midscale 05856-052 figure 44. 0.1 hz to 10 hz output noise plot, 2.5 v internal reference 4s/div 5v/div 1 v dd = 3v v refout = 1.25v t a = 25c dac loaded with midscale 05856-053 figure 45. 0.1 hz to 10 hz output noise plot,1.25 v internal reference
preliminary technical data ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. pra. | page 17 of 32 frequency (hz) output noise (nv/ hz) 800 0 100 200 300 400 500 600 700 100 10k 1k 100k 1m v dd = 3v v refout = 1.25v v dd = 5v v refout = 2.5v t a = 25c midscale loaded 0 5856-054 figure 46. noise spectral density, internal reference frequency (hz) (db) ? 20 ?50 ?80 ?30 ?40 ?60 ?70 ?90 ?100 2k 4k 6k 8k 10k v dd = 5v t a = 25c dac loaded with full scale v ref = 2v 0.3v p-p 0 5856-055 figure 47. total harmonic distortion capacitance (nf) time (s) 16 14 12 10 8 6 4 012 34567 9 810 v ref = v dd t a = 25c v dd = 5v v dd = 3v 0 5856-056 figure 48. settling time vs. capacitive load frequency (hz) (db) 5 ?40 10k 100k 1m 10m ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 v dd = 5v t a = 25c 05856-057 figure 49. multiplying bandwidth
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 18 of 32 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. zero-code error zero-code error is a measurement of the output error when zero scale (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero-code error is always positive in the ad5665r because the output of the dac cannot go below 0 v due to a combination of the offset errors in the dac and the output amplifier. zero-code error is expressed in mv. full-scale error full-scale error is a measurement of the output error when full- scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full-scale error is expressed in percent of full-scale range. gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal expressed as % of fsr. zero-code error drift this is a measurement of the change in zero-code error with a change in temperature. it is expressed in v/c. gain temperature coefficient this is a measurement of the change in gain error with changes in temperature. it is expressed in ppm of fsr/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error is measured on the ad5665r with code 512 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in db. v ref is held at 2 v, and v dd is varied by 10%. output voltage settling time this is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full-scale input change and is measured from the rising edge of the stop condition. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s, and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000) (see figure). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv-s, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated. it is expressed in db. noise spectral density this is a measurement of the internally generated random noise. random noise is characterized as a spectral density (nv/ hz). it is measured by loading the dac to midscale and measuring noise at the output. it is measured in nv/ hz. a plot of noise spectral density can be seen in figure . dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac (or soft power-down and power-up) while monitoring another dac kept at midscale. it is expressed in v. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in v/ma. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv-s.
preliminary technical data ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. pra. | page 19 of 32 analog crosstalk this is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa). then execute a software ldac and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv-s. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent analog output change of another dac. it is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa) using the command write to and update while monitoring the output of the victim channel that is at midscale. the energy of the glitch is expressed in nv-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measurement of the harmonics present on the dac output. it is measured in db.
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 20 of 32 theory of operation d/a section the ad5625r/ad5645r/ad5665r, ad5625/ad5665 dacs are fabricated on a cmos process. the architecture consists of a string dac followed by an output buffer amplifier. figure 50 shows a block diagram of the dac architecture. dac register ref (+) resistor string ref (-) gnd output amplifier gain = +2 v out v dd figure 50. dac architecture because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n refin out d v v 2 the ideal output voltage when using the internal reference is given by ? ? ? ? ? ? = n refout out d v v 2 2 where: d is the decimal equivalent of the binary code that is loaded to the dac register: 0 to 4095 for ad5625r/ad5625 (12 bit). 0 to 16,383 for ad5645r (14 bit). 0 to 65,535 for ad5665r/ad5665 (16 bit). n is the dac resolution. resistor string the resistor string is shown in figure 51. it is simply a string of resistors, each of value r. the code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. output amplifier the output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 v to v dd . it can drive a load of 2 k in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figure and figure. the slew rate is 1.8 v/s with a ? to ? full-scale settling time of 7 s. to output amplifier r r r r r figure 51. resistor string internal reference the ad5625r/ad5645r/ad5665r feature an on-chip reference. versions without the Cr suffix require an external reference. the on-chip reference is off at power-up and is enabled via a write to a control register. see the internal reference setup section for details. versions packaged in 10-lead lfcsp package have a 1.25 v reference, giving a full scale output of 2.5 v. these parts can be operated with a vdd supply of 2.7v to 5.5v. versions packaged in 14-lead tssop package have a 2.5 v reference, giving a full- scale output of 5 v. parts are functional with a vdd supply of 2.7v to 5.5v but for vdd supply of less than 5v, the output will be clamped to vdd. see the ordering information on the back page for a full list of models. the internal reference associated with each part is available at the v refout pin. a buffer is required if the reference output is used to drive external loads. when using the internal reference, it is recommended that a 100 nf capacitor is placed between reference output and gnd for reference stability. external reference the v refin pin on the ad56x5r allows the use of an external reference if the application requires it. the default condition of the on-chip reference is off at power-up. all devices can be operated from a single 2.7 v to 5.5 v supply. serial interface the ad5625r/ad5645r/ad5665r, ad5625/ad5665 have 2- wire i 2 c-compatible serial interfaces (refer to i 2 c-bus specification , version 2.1, january 2000, available from philips semiconductor). the ad5625r/ad5645r/ad5665r, ad5625/ad5665 can be connected to an i 2 c bus as a slave device, under the control of a ma ster device. see figure 2 for a timing diagram of a typical write sequence.
preliminary technical data ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. pra. | page 21 of 32 the ad5625r/ad5645r/ad5665r, ad5625/ad5665 support standard (100 khz), fast (400 kh z), and high speed (3.4 mhz) data transfer modes. high-speed operation is only available on selected models. see the ordering information on the back page for a full list of models. support is not provided for 10-bit addressing and general call addressing. the ad5625r/ad5645r/ad5665r, ad5625/ad5665 each have a 7-bit slave address. 10-pin versions of the part have a slave address whose five msbs are 00011, and the two lsbs are set by the state of the addr a ddress pin, which determines the state of the a0 and a1 address bits. 14-pin versions of the part have a slave address whose thre e msbs are 001, and the four lsbs are set by the addr1 and addr2 address pins, which determine the state of the a0 and a1, a2 and a3 address bits respectively. the addr pin is three-state, and can be set as shown in table 8 to give three different addresses. table 8. addr pin settings (10-pin package) addr pin connection a1 a0 vdd 0 0 no connection 1 0 gnd 1 1 the addr1 and addr2 pins are al so three-state, and can be set as shown in table 9 to give a total of 9 different addresses. table 9. addr1, addr2 pin setting (14-pin package) addr2 addr1 a3 a2 a1 a0 vdd vdd 0 0 0 0 vdd nc 0 0 1 0 vdd gnd 0 0 1 1 nc vdd 1 0 0 0 nc nc 1 0 1 0 nc gnd 1 0 1 1 gnd vdd 1 1 0 0 gnd nc 1 1 1 0 gnd gnd 1 1 1 1 the 2-wire serial bus protocol operates as follows: 1. the master initiates data tr ansfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7-bit slave address. the slave address corresponding to the transmitted address responds by pulling sda low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read or written, a stop condition is established. in wr ite mode, the master pulls the sda line high during the 10th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the 10th clock pulse, and then high during the 10th clock pulse to establish a stop condition.
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 22 of 32 r/w 0 scl sda 0 0 1 1 a1 a0 db23 db22 db21 db20 db19 db18 db17 db16 ack. by ad56x5 start by master frame 1 slave address frame 2 command byte 191 ack. by ad56x5 9 db7 db6 db5 db4 db3 db2 db1 db0 ack. by ad56x5 stop by master 19 9 scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 ack. by ad56x5 1 frame 3 most significant data byte frame 4 least significant data byte figure 52. i 2 c write operation (10-pin package) r/w 0 scl sda 01 a1a0 db23 db22 db21 db20 db19 db18 db17 db16 ack. by ad56x5 start by master frame 1 slave address frame 2 command byte 191 ack. by ad56x5 9 db7 db6 db5 db4 db3 db2 db1 db0 ack. by ad56x5 stop by master 19 9 scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 ack. by ad56x5 1 a3 a2 frame 3 most significant data byte frame 4 least significant data byte figure 53. i 2 c write operation (14-pin package) write operation when writing to th e ad5625r/ad5645r/ad5665r, ad5625/ad5665, the user must begin with a start command followed by an address byte (r/w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. the ad5665 requires two bytes of data for the dac and a command byte that controls va rious dac functions. three bytes of data must therefore wr itten to the dac, the command byte followed by the most signif icant data byte and the least significant data byte, as shown in figures 52 and 53. all these data bytes are acknowledged by the ad5625r/ad5645r/ad5665r, ad5625/ad5665. a stop condition follows. read operation when reading data back from the ad5625r/ad5645r/ad5665r, ad5625/ad5665, the user begins with a start command followed by an address byte (r/w = 1), after which the dac acknowle dges that it is prepared to transmit data by pulling sda low. two bytes of data are then read from the dac, which are both acknowledged by the master as shown in figures 54 and 55. a stop condition follows. note that the only data that ca n be read back from the ad56x5 is the contents of the input shift register (see section on control register).
preliminary technical data ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. pra. | page 23 of 32 r/w 0 scl sda 0 0 1 1 a1 a0 db23 db22 db21 db20 db19 db18 db17 db16 ack. by master start by master frame 1 slave address frame 2 command byte 191 ack. by ad56x5 9 db7 db6 db5 db4 db3 db2 db1 db0 no ack. stop by master 19 9 scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 ack. by master 1 frame 3 most significant data byte frame 4 least significant data byte figure 54. i 2 c read operation(10-pin package) r/w 0 scl sda 0 1 a1 a0 db23 db22 db21 db20 db19 db18 db17 db16 ack. by master start by master frame 1 slave address frame 2 command byte 191 ack. by ad56x5 9 db7 db6 db5 db4 db3 db2 db1 db0 no ack. stop by master 19 9 scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 ack. by master 1 frame 3 most significant data byte frame 4 least significant data byte a3 a2 figure 55. i 2 c read operation(14-pin package) high speed mode some models offer high-speed serial communication with a clock frequency of 3.4 mhz. see the ordering information on the back page for a full list of models. high speed mode communication commences after the master addresses all devices connected to the bus with the master code 00001xxx to indicate that a high speed mode transfer is to begin. no device connected to the bus is permitted to acknowledge the high speed master code, therefore, the code is followed by a no acknowledge. the master must then issue a repeated start followed by the device address. the selected device then acknowledges its address. all devices continue to operate in high speed mode until the master issues a stop condition. when the stop condition is issued, the devices return to standard/fast mode. th e part will also exit high speed mode if clr is activated while part is in high speed mode.. 0 scl sda 0 0 1 x x 0 0 0 1 1 a1 a0 start by master hs-mode master code serial bus address byte* 191 9 ack. by ad56x5 0 x nack sr r/w fast mode high-speed mode *note: address shown is for 10-pin device. address for 14-pin device is 001(a3)(a2)(a1)(a0) figure 56. placing the ad56x5 in high-speed mode
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 24 of 32 multiple byte write once an ad56x5 has been addressed, one or more three-byte blocks of command and data can be sent to the device, until a stop condition is received. th e device must then be re- addressed. for this type of operation, the s bit in the command byte is set to zero. for some types of application su ch as waveform generation, it may be required to update a dac or dacs as fast as possible without changing the command byte. in this case the s bit in the initial command byte is set to 1. this sets the command parameters for all subsequent da ta. thereafter, multiple two- byte blocks of data high byte and data low byte can be sent, without sending a further command byte, until a stop condition is received. the s bit is only active in the first command byte following the device slave address. therefore , even if the s bit is 0 and three-byte blocks of command and da ta are being sent, it is not possible to alter the multi-byte mo de by changing the s bit to 1 on-the-fly during any subsequent command byte. stop least significant data byte most significant data byte command byte block 1 s=0 slave address least significant data byte most significant data byte command byte block 2 s=0 least significant data byte most significant data byte command byte block n s=0 figure 57. multiple block write with command byte in each block (s=0) stop least significant data byte most significant data byte command byte block 1 s=1 slave address least significant data byte most significant data byte block 2 s=1 least significant data byte most significant data byte block n s=1 figure 58. multiple block write with initial command byte only (s=1) broadcast mode in addition to the unique slave address for each device, which is set by the address pin(s), the ad56x5 has a broadcast address to which any ad56x5 will respond, irrespective of the state of the address pin(s). this a ddress is 0001000(write). where several ad56x5 devices are connected to a bus, they can all be sent the same data using the br oadcast address. the broadcast address only works for write oper ations. it is not possible to read back data from several devi ces at the same time, due to bus contention. input shift register the input shift register is 24 bits wide to store the 3 data bytes written to the device of the serial interface. data written to the device is split into four sections: - one bit to select multiple byte operation. - a three bit command that tells the device what operation to perform. - a three-bit address that tells the device to which dac or dacs the command applies. - 16 bits of data, which, depending on the command may be written to a dac or used to define the parameters of a command operation. bit 23 of the input shift register is reserved, and should always be set to 0 when writing to the device. the command and address are contained in the command byte, the 8 msbs of the input register. the middle 8 bits are the high byte of the dac data, while the 8 least significant bits are the low byte of the dac data or command data. dac data is left justified, so the two lsbs are unused for the 14 bit ad5645r, and the four lsbs are unused for the 12-bit ad5625r (but they are still used for command data in these devices. the ad56x5 has seven different commands that can be written to it. c2 c1 c0 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d2 d3 d1 d0 s r r e s e r v e d b y t e s e l e c t i o n command dac address dac data dac or command data command byte data high byte data low byte db23 db22 db21 db20 db19 db18 db1 7 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 figure 59. ad5665r/ad5665 input shift register (16-bit dac)
preliminary technical data ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. pra. | page 25 of 32 c2 c1 c0 a2 a1 a0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d2 d3 d1 d0 s r r e s e r v e d b y t e s e l e c t i o n command dac address dac data dac or command data command byte data high byte data low byte db23 db22 db21 db20 db19 db18 db1 7 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 x x figure 60. ad5645r input shift register (14-bit dac) c2 c1 c0 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d2 d3 d1 d0 s r r e s e r v e d b y t e s e l e c t i o n command dac address dac data dac or command data command byte data high byte data low byte db23 db22 db21 db20 db19 db18 db1 7 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 x x x x figure 61. ad5625r/ad5625 input shift register (12-bit dac) write commands and ldac table 10. command definition c2 c1 c0 command 0 0 0 write to input register n 0 0 1 update dac register n 0 1 0 write to input register n, update all (software ldac) 0 1 1 write to and update dac channel n 1 0 0 power up/power down 1 0 1 reset 1 1 0 ldac register setup 1 1 1 internal reference setup (on/off ) table 10 is the truth table f or the command bits. the dac or dacs on which a command is performed is/are defined by n, which is the dac address shown in table 11. some commands required additional data which is defined in the low data byte. table 11. dac address command a2 a1 a0 address ( n ) 0 0 0 dac a 0 0 1 dac b 0 1 0 dac c 0 1 1 dac d 1 1 1 all dacs the ad5625r/ad5645r/ad5665r, ad5625/ad5665 dacs have double-buffered interfaces consisting of two banks of registers: input registers and dac registers. the input registers are connected directly to the inpu t shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. the dac registers contain the digital code used by the resistor strings. the double-buffered interface is useful if the user requires simultaneous updating of all dac outputs. for example, the user could write to three of the input registers individually and then write to the remaining inpu t register and, updating all dac registers, the outputs will update simultaneously. the ad56x5 has a powerful set of commands for writing to and updating the dacs. the 14-pin version also has a hardware load dac ( ldac ) pin. it is important to understand how these commands and the ldac pin operate and interact with each other, in order to ensure that the desired result is obtained. the first four commands are used for writing to and updating the dacs. command 000 writes to input regi ster n, without updating the dac registers, where n is the input register defined by the a2 -- - a0 bits in the command byte. de pending on the value of a2 -- - a0, this can be any one of the input registers or all four input registers, as defined b y the dac address. command 001 does not write to the input registers, but (depending on the value of a2 -- - a0) updates a dac register or all four dac registers. command 010 writes to input regi ster n, and updates all dac registers. command 011 writes to input register n and updates dac register n. since n can be all dacs (a2 -- - a0 = 111) commands 010 and 011 are equivalent if a2 -- - a0 = 111. ldac setup in addition to the write commands, the ldac setup command (110) can also determine which da cs are updated at the end of a write operation (this comman d does not update the dacs when it is implemented). it also affects the operation of the
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 26 of 32 ldac pin on the 14-pin device (see below). when this command is sent to the device, data bits db3 to db0 determine which of dac registers d through a are updated at the end of write. if a bit is set to 1, th e corresponding dac is updated. note that, during the ldac se tup command, the dac address bits a2 C a0 are ignored. it is only db3 to db0 that determine which dac will be updated. as far as dac updating is co ncerned, the wr ite command and the ldac setup command are combined (ord together). for example, if the ldac setup command is set to update dacs b and d, and command 011 is sent to write to and update dac a, then dac a will be written to, but dacs a, b and d will be updated. 1 1 0a2a1a0x xxxx xxxxx command dac address (don?t care) c2 c1 c0 a2 a1 a0 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db2 db3 db1 db0 don?t care r s x 0 don?t care daca dacd dacc dacb don?t care dac select (0 = ldac pin enabled) x x res figure 62. ldac setup command ldac pin in the case of the 14-pin device, updating of the dac registers may also be controlled by the ldac pin. this can operate either synchronously or asynchronously. whenever ldac is brought low, the dac registers are updated with the contents of the input registers. if ldac is held low, update takes place synchronously at the end of every write operation. which dac registers are updated when ldac is brought low is determined by the ldac setup command. it is the inverse of those registers that are set to upda te at the end of write. if one of bits db3 to db0 is a 0, then the corresponding dac is updated when ldac is taken low. if it is a 1, the dac is updated at the end of a write operation. this allows some dacs to be updated automatically at th e end of write, and some to be updated asynchronously using the ldac pin. if ldac is permanently held low for synchronous update, then all dacs will be updated irrespective of the dac address in the write command or the bit settings in the ldac setup command. this is because those dacs whose bits are 0 in ldac setup will be updated due to the ldac pin being low, and those dacs whose bits are 1 will be updated due to the ldac setup command. if dac update is to be controlle d solely by the write and ldac setup commands, the ldac pin must be tied high (or use the 10-pin device which does not have this pin). if dac update is to be controlled solely by the ldac pin, then use only command 000 and set db3 to db 0 to 0 in the ldac setup command. these parts each contain an extra feature whereby a dac register is not updated unless its input register has been updated since the last time ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the input registers. in the case of the ad56x5, the dac register updates only if the input register has changed since the last time the dac register was updated, thereby removing unnecessary digital crosstalk. power-down modes 1 0 0a2a1a0x xxxx xxxxx command dac address (don?t care) c2 c1 c0 a2 a1 a0 db15 db14 db13 db1 2 db11 db10 db9 db8 db7 db6 db5 db4 db2 db3 db1 db0 don?t care r s x 0 don?t care daca pd1 pd0 dacd dacc dacb don?t care power down mode dac select (1 = dac selected) res figure 63. power up/down command command 100 is the power up/dow n function. the parameters of the power up/down function are programmed by bits db5 and db4. this defines the output state of the dac amplifier, as shown in table 12. bits db3 to db0 determine to which dac or dacs the power up/down command is applied. setting the one of these bits to 1 applies the power up/down state defined by db5 and db4 to the correspondi ng dac. if a bit is 0, the state of the dac is unchanged. in power-down mode, the amplif ier is disconnected from the output pin, and the output pin is either open-circuit or connected ground via a 10k ? or 100k ? resistor, depending on the setting of db5 and db4. table 12. modes of operation for the ad5625r/ad5645r/ad5665r, ad5625/ad5665 db5 db4 operating mode 0 0 normal operation
preliminary technical data ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. pra. | page 27 of 32 power-down modes 0 1 1 k? pulldown to gnd 1 0 100 k? pulldown to gnd 1 1 three-state, high impedance resistor network v out resistor string dac power-down circuitry amplifier 05856-038 figure 64. output stage during power-down the bias generator, the output amplifier, the resistor string, and other associated linear circuitry are shutdown when power- down mode is activated. however, the contents of the dac register are unaffected when in power-down. the time to exit power-down is typically 4 s for v dd = 5 v and for v dd = 3 v. figure 63 shows the format of the power up/down command. note that, during the power up/down command, the dac address bits a2 C a0 are ignored. power-on-reset and software reset the ad56x5 contains a power-on reset circuit that controls the output voltage during power-up. the 10-pin version of the device powers up to 0v. the 14-pin version has a power on reset (por) pin that allows the output voltage to be selected. by connecting the por pin low, the ad56x5 output powers up to 0 v; by connecting the por pin high, the ad56x5 output powers up to midscale. the output remains powered up at this level until a valid write sequence is made to the dac. this is useful in applications where it is important to know the state of the output of the dac while it is in the process of powering up. any events on ldac or clr during power-on reset are ignored. there is also a software reset function. command 101 is the software reset command. the software reset command contains two reset modes that are software programmable by setting bit db0 in the input shift register. table 13 shows how the state of the bit corresponds to the software reset modes of operation of the devices. figure 64 shows the contents of the input shift register during the software reset mode of operation. table 13. software reset modes for the ad5625r/ad5645r/ad5665r, ad5625/ad5665 db0 registers reset to zero 0 dac register input shift register 1 (power-on reset) dac register input shift register ldac register power-down register internal reference setup register clear pin ( clr ) the 14-pin version of the ad56x5 has an asynchronous clear input. the clr input is falling edge sensitive. while clr is low, all ldac pulses are ignored. when clr is activated, zero scale is loaded to all input and dac registers. this clears the output to 0 v. the part exits clear code mode on the 24th falling edge of the next write to the part. if clr is activated during a write sequence, the write is aborted. if clr is activated during high speed mode the part will exit high speed mode to fast mode. figure 65. reset command internal reference setup (-r versions) the on-chip reference is off at power-up by default. it can be turned on by sending the reference setup command (111) and setting db0 in the input shift register. table 14 shows how the state of the bit corresponds to the mode of operation. table 14. reference setup command (db0) action 0 internal reference off (default) 1 internal reference on
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 28 of 32 figure 66. reference setup command
preliminary technical data ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. pra. | page 29 of 32 applications using a reference as a power supply for the ad5625r/ad5645r/ad5665r, ad5625/ad5665 because the supply current required by the ad5625r/ad5645r/ad5665r, ad5625/ad5665is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see figure). this is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 v or 3 v, for example, 15 v. the voltage reference outputs a steady supply voltage for the ad5625r/ad5645r/ad5665r, ad5625/ad5665. if the low dropout ref195 is used, it must supply 450 a of current to the ad5625r/ad5645r/ad5665r, ad5625/ad5665 with no load on the output of the dac. when the dac output is loaded, the ref195 also needs to supply the current to the load. the total current required (with a 5 k? load on the dac output) is 450 a + (5 v/5 k?) = 1.45 ma the load regulation of the ref195 is typically 2 ppm/ma, resulting in a 2.9 ppm (14.5 v) error for the 1.45 ma current drawn from it. this corresponds to a 0.191 lsb error. ref195 2-wire serial interface scl sda v dd ad5625(r)/ ad5645r/ ad5665(r) v out =0vto5v gnd 1 5 v 5v figure 67. ref195 as power supply to the ad5625r/ad5645r/ad5665r, ad5625/ad5665 bipolar operation using the ad5625r/ad5645r/ad5665r, ad5625/ad5665 the ad5625r/ad5645r/ad5665r, ad5625/ad5665 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 67. the circuit gives an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. the output voltage for any input code can be calculated as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = r1 r2 v r1 r2 r1 d v v dd dd o 536 , 65 where d represents the input code in decimal (0 to 65535). with v dd = 5 v, r1 = r2 = 10 k?, v 5 536 , 65 10 ? ? ? ? ? ? ? = d v o this is an output voltage range of 5 v, with 0x0000 corre- sponding to a ?5 v output, and 0xffff corresponding to a +5 v output. 2-wire serial interface scl sda v dd gnd +5v 10f 0.1f ad5625(r)/ ad5645r/ ad5665(r) v out r1 = 10k ? r2 = 10k ? +5v -5v ad820/ op295 5v figure 68. bipolar operation wi th the ad5625r/ad5645r/ad5665r, ad5625/ad5665 power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad5625r/ad5645r/ad5665r, ad5625/ad5665 should have separate analog and digital sections, each having its own area of the board. if the ad5625r/ad5645r/ad5665r, ad5625/ad5665 are in a system where other devices require an agnd-to-dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5625r/ad5645r/ad5665r, ad5625/ad5665. the power supply to the ad5625r/ad5645r/ad5665r, ad5625/ad5665 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be located as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitor is the tantalum bead type. it is important that the 0.1 f capacitor have low effective series resistance (esr) and effective series inductance (esi), for example, common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2-layer board.
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 30 of 32
preliminary technical data ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. pra. | page 31 of 32 outline dimensions 3.00 bsc sq index area top view 1.50 bcs sq exposed pad (bottom view) 1.74 1.64 1.49 2.48 2.38 2.23 1 6 10 0.50 bsc 0.50 0.40 0.30 5 pin 1 indicator 0.80 0.75 0.70 0.05 max 0.02 nom s eating plane 0.30 0.23 0.18 0.20 ref 0.80 max 0.55 typ side view figure 69. 10-lead lead frame chip scale package [lfcsp_wd] 3 mm x 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc seating plane 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 8 0 0.75 0.60 0.45 coplanarity 0.10 compliant to jedec standards mo-153-ab-1 figure 70. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters
ad5625r/ad5645r/ad5665r , ad5625/ad5665 preliminary technical data rev. pra. | page 32 of 32 ordering guide model temperature range accuracy on-chip reference max i 2 c speed package description package option branding ad5625bcpz-250rl7 1 ?40c to +105c 1 lsb inl none 400 khz 10-lead lfcsp_wd cp-10 -9 d8v ad5625bcpz-reel7 1 ?40c to +105c 1 lsb inl none 400 khz 10-lead lfcsp_wd cp-10-9 d8v ad5625bruz 1 ?40c to +105c 1 lsb inl none 400 khz 14-lead tssop ru-14 none ad5625bruz-reel7 1 ?40c to +105c 1 lsb inl none 400 khz 14-lead tssop ru-14 none ad5625rbcpz-250rl7 1 ?40c to +105c 1 lsb inl 1.25 v 400 khz 10-lead lfcsp_wd cp-10-9 d8s ad5625rbcpz-reel7 1 ?40c to +105c 1 lsb inl 1.25 v 400 khz 10-lead lfcsp_wd cp-10-9 d8s ad5625rbruz-1 1 ?40c to +105c 1 lsb inl 2.5 v 400 khz 14-lead tssop ru-14 none ad5625rbruz-1reel7 1 ?40c to +105c 1 lsb inl 2.5 v 400 khz 14-lead tssop ru-14 none ad5625rbruz-2 1 ?40c to +105c 1 lsb inl 2.5 v 3.4 mhz 14-lead tssop ru-14 none ad5625rbruz-2reel7 1 ?40c to +105c 1 lsb inl 2.5 v 3.4 mhz 14-lead tssop ru-14 none ad5645rbcpz-250rl7 1 ?40c to +105c 4 lsb inl 1.25 v 400 khz 10-lead lfcsp_wd ru-14 d89 ad5645rbcpz-reel7 1 ?40c to +105c 4 lsb inl 1.25 v 400 khz 10-lead lfcsp_wd ru-14 d89 ad5645rbruz 1 ?40c to +105c 4 lsb inl 2.5 v 400 khz 14-lead tssop ru-14 none ad5645rbruz-reel7 1 ?40c to +105c 4 lsb inl 2.5 v 400 khz 14-lead tssop ru-14 none ad5665bcpz-250rl7 1 ?40c to +105c 16 lsb inl none 400 khz 10-lead lfcsp_wd cp-10-9 d6u ad5665bcpz-reel7 1 ?40c to +105c 16 lsb inl none 400 khz 10-lead lfcsp_wd cp-10-9 d6u ad5665bruz 1 ?40c to +105c 16 lsb inl none 400 khz 14-lead tssop ru-14 none ad5665bruz-reel7 1 ?40c to +105c 16 lsb inl none 400 khz 14-lead tssop ru-14 none ad5665rbcpz-250rl7 1 ?40c to +105c 16 lsb inl 1.25 v 400 khz 10-lead lfcsp_wd cp-10-9 da2 ad5665rbcpz-reel7 1 ?40c to +105c 16 lsb inl 1.25 v 400 khz 10-lead lfcsp_wd cp-10-9 da2 ad5665rbruz-1 1 ?40c to +105c 16 lsb inl 2.5 v 400 khz 14-lead tssop ru-14 none ad5665rbruz-1reel7 1 ?40c to +105c 16 lsb inl 2.5 v 400 khz 14-lead tssop ru-14 none AD5665-RBRUZ-2 1 ?40c to +105c 16 lsb inl 2.5 v 3.4 mhz 14-lead tssop ru-14 none ad5665rbruz-2reel7 1 ?40c to +105c 16 lsb inl 2.5 v 3.4 mhz 14-lead tssop ru-14 none 1 z = pb-free part.

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